Karthik Nagarajan

PhD Student, Department of Electrical and Computer Engineering
Office: NEB 458

Prediction of stream flow based on physical models that relate various parameters (rainfall, contributing area, terrain features) to flow is problematic, in that the parameters are non-stationary, both spatially and temporally. This necessitates the need to specify a variety of boundary conditions which might be difficult because of the inability to measure the parameters in sufficient spatial and temporal detail. Purely statistical approaches to the prediction of stream flow via regression with rainfall and terrain features have also been widely investigated. But, it too often gives suboptimal performances owing to the fact that one set of estimated parameters for a test site might not suit a different site (or a different time). While stream flows at discrete points can be directly measured, quantitative study of entire watersheds and sub-basins has been plagued by the lack of dense set of in situ sensors or a framework to merge point measurements and distributed information. My research work involves using concepts in pattern recognition, information theory, graphical models and multiscale estimation to solve the problem in a probabilistic framework. I am closely involved in an NSF-funded Hydrology project over the Santa Fe basin, studying stream flow and transport of minerals through the watershed system.

Flow estimation using Spatio-Temporal Bayesian Networks

Performing machine learning algorithms over dense datasets (over million points) is a computationally intensive task on general purpose processors. FPGAs and the field of “High Performance Computing” have been applied to computationally intensive problems in various domains mainly addressing speedup issues. However, there is still a significant need of in-depth research and proof of success with real applications for proposing them as solutions for a more general class of problems. Since developing FPGA designs is time-consuming, undertaking an exhaustive design process for every algorithm is also not a feasible option. A more practical approach involves the understanding of common patterns in terms of computational structure and data flow across a variety of algorithms and proving that those design patterns are indeed suitable and reusable for an FPGA implementation. A pattern-based design methodology for implementing algorithms on FPGAs can lead to a significant increase in productivity via design reusability. Quantifying design patterns also aids in exploiting the performance prediction tool, RAT, to predict an algorithm’s amenability to a hardware platform before undertaking a lengthy development process. Along this line, I conduct research on the design, analysis and development of complex algorithms on FPGAs as a student member of the NSF-funded center called CHREC (NSF Center for High-Performance Reconfigurable Computing) at UF.

Decomposition of algorithms for parallel implementation on FPGAs using Design Patterns